This invention relates to digital DLL (delay lock loop) circuits. More particularly, this invention relates to low pass filters in digital delay lock loop circuits.
Digital delay lock loop circuits typically generate a clock signal based on a periodic reference signal (e.g., from an oscillator) that maintains a specific phase relationship with that reference signal. Digital delay lock loop circuits are often used, for example, in high-speed clocked memories such as SDRAMs (synchronous dynamic random access memories).
A digital delay lock loop circuit usually includes a phase detector that detects a phase difference outside the specified phase relationship between the periodic reference signal and the periodic output signal, which is fed back to the phase detector. The phase detector provides a “shift” signal, if necessary, to adjust the phase of the output signal. Such shift signals cause the delay between output signal transitions and corresponding reference signal transitions to increase or decrease as needed to reestablish the specified phase relationship.
However, phase detectors may erroneously provide shift signals in response to noise on the phase detector inputs, rather than in response to an actual phase difference between the reference signal and the output signal. This can cause errors in the output signal. For example, transient noise in a delay lock loop circuit may cause the output signal to unnecessarily shift even though the output signal is tracking the reference signal accurately. After the output signal shifts, it may no longer be within the specified phase relationship with the reference signal. This can cause logic errors in cases where, for example, the output signal is a clock signal shifted out of specification. Moreover, the transient noise is likely to disappear, resulting in the output signal shifting again. At the least, typical delay lock loop circuits can unnecessarily disturb an output signal.
A known solution is to couple a digital low pass filter to the output of the phase detector to prevent shifts caused by high frequency noise from propagating through to the output signal. However, these filters become relatively large and cumbersome as the low pass frequency is lowered, and thus, are not always practical.
In view of the foregoing, it would be desirable to provide a digital delay lock loop circuit having a versatile, compact low pass filter that reduces, if not prevents, the adverse effects of input noise.